Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique
Received: 27 September 2025 | Revised: 6 November 2025 and 17 November 2025 | Accepted: 22 November 2025 | Online: 4 April 2026
Corresponding author: N. Shylashree
Abstract
Dynamic Random-Access Memory (DRAM) is a key element in high-performance digital systems, but conventional designs suffer from high power dissipation and latency. This paper presents three new FinFET-based DRAM cell architectures: a two-transistor (2T) DRAM and two three-transistor (3T) DRAM configurations, each of which incorporates sleep transistors to enhance energy efficiency. The proposed designs aim to optimize read and write delay while reducing both dynamic and short-circuit power consumption. FinFET devices improve switching speed, and the inclusion of sleep transistors effectively minimizes leakage, enabling lower overall energy use. Circuit-level simulations were carried out in the Cadence Virtuoso Analog Design Environment. The results demonstrate that the proposed 2T-DRAM achieves a 66% reduction in write delay, while the 3T-DRAM achieves up to 98% improvement in read delay. Power consumption decreases by up to 99.6% during writing and 99.8% during reading operations compared to conventional DRAM cells. These outcomes highlight the effectiveness of the proposed FinFET-based DRAM architectures for compact, low-power on-chip memory applications.
Keywords:
DRAM, 2T-DRAM, 3T-DRAM, power, delayDownloads
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