ANURADHA, M. G.; ARUN KUMAR, R. A Novel and Efficient Left-to-Right Binary Adder Architecture for reduced Area and Power Metrics in VLSI Design. Engineering, Technology & Applied Science Research, Greece, v. 15, n. 3, p. 22629–22635, 2025. DOI: 10.48084/etasr.9840. Disponível em: https://mail.etasr.com/index.php/ETASR/article/view/9840. Acesso em: 22 may. 2026.