Deepika P, Shylashree N. Design of an Array Multiplier for Computation in Memory Architecture. Eng. Technol. Appl. Sci. Res. [Internet]. 2025 Oct. 6 [cited 2026 May 18];15(5):27285-92. Available from: https://mail.etasr.com/index.php/ETASR/article/view/11806