Gowreesrinivas KV, Srinivas S, Samundiswary P. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders. Eng. Technol. Appl. Sci. Res. [Internet]. 2023 Jun. 2 [cited 2025 May 20];13(3):10698-702. Available from: https://mail.etasr.com/index.php/ETASR/article/view/5797